![]() U1_N_bit_adder : N_bit_adder generic map ( N => 16) - ABUS + BBUS port map( input1 => ABUS, input2 => BBUS,answer => tmp_out1 ) Signal tmp : std_logic_vector( 16 - 1 downto 0) īegin - instantiate Verilog N-bit Adder in VHDL code Signal tmp_out2 : std_logic_vector( 16 - 1 downto 0) Signal tmp_out1 : std_logic_vector( 16 - 1 downto 0) Signal BBUS_not : std_logic_vector( 16 - 1 downto 0) Input2 : in std_logic_vector(N - 1 downto 0) Īnswer : out std_logic_vector(N - 1 downto 0) Port( input1 : in std_logic_vector(N - 1 downto 0) : FPGA projects, Verilog projects, VHDL projects - VHDL project: VHDL code for 16-bit ALU - Top level VHDL code for 16-bit ALU library IEEE ĪBUS : in std_logic_vector( 15 downto 0) - ABUS data input of the 16-bit ALUīBUS : in std_logic_vector( 15 downto 0) - BBUS data input of the 16-bit ALUĪLUctrl : in std_logic_vector( 3 downto 0) - ALUctrl control input of the 16-bit ALUĪLUOUT : out std_logic_vector( 15 downto 0) - 16-bit data output of the 16-bit ALUĪrchitecture Behavioral of ALU is - N-bit Adder in Verilog component N_bit_adder is generic (
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